1. Field of the Invention
This invention relates to a random access memory device and more particularly, a method for fabricating a stacked storage capacitor with vertical sidewalls having increased capacitance.
2. Description of the Prior Art
Very large scale integration (VLSI) semiconductor technologies have dramatically increased the circuit density on a chip. The miniaturized devices built in and on semiconductor substrate, making up these circuits, are very closely spaced and their packing density has increased significantly. More recent advances in photolithographic techniques, such as phase-shifting masks, and self-aligning process steps have further reduced the device size and increased circuit density. This has lead to ultra large scale integration (ULSI) with minimum device dimensions less than a micrometer and more than a million transistors on a chip. With this improved integrations, some circuit elements experience electrical limitation due to their down sizing.
One such circuit element experiencing electrical limitations is the array of storage cells on a dynamic random access memory (DRAM) chip. These individual DRAM storage cells, usually consisting of a single metal-oxide-semiconductor field-effect-transistor (MOSFET) and a single capacitor are used extensively in the electronic industry for storing data. A single DRAM cell stores a bit of data on the capacitor as electrical charge.
As the array of cells on the DRAM chip increase in number and the capacitor decreases in size. It becomes more difficult to maintain an acceptable signal-to-noise level. Also, these volatile storage cells require more frequent refresh cycles to retain their charge.
These storage capacitors can be formed either in the substrate, usually referred to as trench capacitor, or by forming a stacked capacitor on the substrate after first fabricating the MOSFET. The latter approach has received considerable attention in recent years. However, since each stacked capacitor, in the array of cells, are confined within the cell area it is difficult to maintain sufficient capacitance, as the cell size decreases. As conventional methods of high resolution photolithography and anisotropic etching reach their limits, it becomes necessary to explore other methods for increasing the capacitance.
One method of increasing the capacitance is to roughen the surface of the bottom electrode of the capacitor to effectively increase the surface area without increasing its overall size. See, for example, H. C. Tuan et.al. U.S. Pat. No. 5,266,514. Another approach is to use an inter-electrode insulator having a high dielectric constant. See for example, "A Newly Designed Planar Stacked Capacitor Cell with High Dielectric Constant Film for 256 Mbit DRAM" by T. Eimori et al, IEEE International Electronic Device Meeting Proceedings, December 1993 page 631-634. A third approach, which has received much attention, is to build three dimensional capacitor structure extending vertically upward over the cell area. For example, see H-H Tseng, U.S. Pat. No. 5,126,916. In that patent, a free standing insulating sidewall is formed over the cell area. Then the bottom electrode, the inter-electrode dielectric and the top electrode are deposited over the insulator sidewall to form the capacitor. Another approach by P. Fazan et al, U.S. Pat. No. 5,084,405 uses a double sidewall technique to form a double ring stacked cell structure. And in U.S. Pat. No. 5,233,212 M. Ohi et al the vertical sidewall of the capacitor is formed by depositing the capacitor electrode material on the sidewall of a recessed in an insulator. A number of other inventions also teach methods of forming vertical capacitor structures, either by forming multiple sidewalls and/or by timed etching. For example, see C. H. Dennison et al U.S. Pat. No. 5,061,650, S. Matsumoto et al U.S. Pat. No. 5,217,914, and H-H Tseng U.S. Pat. No. 5,192,702.
However, many of these methods require substantially more processing steps or/and planar structures which make the manufacturing process more complex and costly. Also, other process methods rely on etching to a predetermined etch depth which can be quite difficult to control in a manufacturing environment. For example, during plasma etching outgassing, virtual or real leaks, back streaming from pumps and loading effects, to name a few, can change the chemistry of the etching environment in the process chamber, making a calibrated etch time approach difficult to control. Therefore, it is very desirable to develop processes that are as simple as possible and also provide methods for monitoring, in situ, the etch depth during processing.
In the prior art, as shown by the schematic cross-sectional view in FIG. 1-A, a conventional DRAM cell usually has a stacked capacitor with a minimal electrode surface area 2. In more advanced structures of the prior art, as shown in FIG. 1-B, vertical sidewalls 4 are formed to increase the electrode area 6. However, accurate and repeated control of the sidewall spacer height is difficult.